Title :
Low-power MCML circuit with sleep-transistor
Abstract :
This paper proposes a low-power MOS current mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16×16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MOS current model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 ¿m CMOS process. The validity and effectiveness are verified through the HSPICE simulation.
Keywords :
CMOS logic circuits; SPICE; current-mode circuits; current-mode logic; leakage currents; low-power electronics; multiplying circuits; transistor circuits; HSPICE simulation; MOS current mode logic circuit; Samsung CMOS process; leakage current; low-power MCML circuit; parallel multiplier; sleep transistor; voltage transistor; Batteries; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Energy consumption; Frequency; Leakage current; Logic circuits; Voltage; MOS current logic (MCML); arithmetic unit; low-power circuit; multiplier; sleep-transistor;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351614
