Architecture design of variable lengths instructions expansion for VLIW

In current instruction set architecture (ISA) design, fixed length instructions are benefit for improving the efficiency of instruction dispatching. But in embeded computers where memory is limited, variable lengths instructions are much better in memory cost. In this VLIW (very long instruction word) architecture, a two-staged pipeline is used to expand and dispatch the variable lengths instructions. When CPU receives a packet of instructions, a fixed number of instructions expand in the first pipeline phase. In the second pipeline phase, CPU dispatch instructions which execute in the same pipeline cycle.