An IF input continuous-time sigma-delta analog-digital converter with high image rejection

A novel resistor time-sharing technique is proposed to achieve higher image rejection (IR) in the design of an intermediate frequency (IF) continuous time (CT) sigma delta (ΣΔ) modulator with integrated IF mixers. A third order CT ΣΔ modulator with current feedforward compensation is designed, as well as current input comparator, digital tunable clock tree, etc. It is also found that, for the first stage of a modulator, the gain of input signal and feedback signal can be scaled down to relieve the harsh requirement of active components´ input/output swing. This design is implemented in a 0.35 μm double-poly four metal layer CMOS technology. Active area is 0.4 mm² and consumes 14.8 mW from a 3.3 V power supply. Postlayout simulation with 25 MHz IF shows no image signal is present for 4096 output data.