On the Addition of an Input Buffer to an Iterative Decoder for LDPC Codes

This paper describes the application of a new hardware architecture to the design of a decoder for low-density parity-check (LDPC) codes. Thanks to the systematic use of the built-in stopping rule in the decoder, the decoder runs the minimum number of iterations on each packet of received data. The addition of a small buffer on the decoder input allows the exploitation of the variations in the decoding time of different packets, in a spirit similar to statistical multiplexing of the data flow. Analysis and simulations are presented using the decoder for the next generation satellite digital video broadcasting (DVB-S2) as a case study, to show that the throughput may be doubled with only two extra buffer locations, at almost no cost in chip area.