A flexible architecture for multi-standard LDPC decoders

Since low-density parity-check codes have near-capacity decoding performance and very high decoding throughput, they have been employed as FEC coding scheme in many transmission standards for wireless communication, such as IEEE 802.22n, IEEE 802.16e, DVB-S2, and DTMB. This trend triggers the need for so-called multi-standard LDPC decoders. In this paper, a flexible architecture that supports multiple code rates, variable block sizes and is code independent for block-LDPC codes is proposed, based on rearranged TPMP algorithm,. By implementing a dynamically reconfigurable RPPU, our proposed architecture can be configured into row update or column update mode by time-division multiplexing. Consequently, the decoder achieves a high area and power efficiency. To verify our proposed architecture, a novel LDPC decoder which supports IEEE802.16e standard has been implemented. The results on a 0.18 um CMOS process show that the decoder occupies an area of approximately 13.7 mm² and runs correctly at an maximum operating frequency of 110 MHz, resulting in 98 Mbps decoding throughput.