An area efficient multi-mode architecture for reed-solomon decoder

This paper proposes a multi-mode solution that can be implemented in any applications requiring more than one RS code rate. We develop the Multi-Symbol Process Element (PE) in KES part to meet the multi-mode applications requirement and greatly reduce hardware complexity. The Multi-Symbol PE makes KES module simple and regular as well as area efficient. Besides, basic cells of Syndrome Calculation module and Error Correction module are grouped to meet the multi-mode goal. With the method we provided in this paper, a general solution for multi-mode system can be concluded. The synthesis results of VLSI structure under CMMB standard show that it costs only 73,408 gates by SMIC 0.13 ¿m library.