Design and implementation of a multi-mode interleaver/deinterleaver for MIMO OFDM systems

This paper presents a novel design strategy and a new architecture for multi-mode interleaver/deinterleaver, which are capable to implement any of the interleaving processes defined in the IEEE 802.11 a/g/n, 802.16d/e, and HiperLAN/2 wireless standards. To enable a comparison, a 36-mode interleaver/deinterleaver fully compliant to IEEE 802.11n applications is presented. The proposed design is implemented in SMIC 0.13 um 1.08 V 1P6M CMOS technology. The maximum operating frequency is 350 MHz and the corresponding power dissipation is 9.27 mW. The core size is 0.0649 mm². This presented architecture achieves a significant reduction of silicon area and power consumption compared with other current approaches.