A low-power 4K point FFT processor for CMMB OFDM receiver system

Author

Li, Simeng ; Xiao, Hao ; Chen, Yun ; Zeng, Xiaoyang

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

517

Lastpage

520

Abstract

This paper presents a 4096-point FFT processor for CMMB receiver system, in which dual-path pipelined shared memory architecture is employed. With a data reordering for receiver, an elaborate memory configuration scheme, single-port SRAM can be adopted without degrading throughput rate, with small area and lower power dissipation. In addition, the Signal-to-Quantization Noise Ratio (SQNR) of a 4 K-point fixed-point FFT can achieve 48.7 B with the wordlength of 12 bit.

Keywords

OFDM modulation; broadcasting; fast Fourier transforms; receivers; 4K-point fixed-point; China mobile multimedia broadcasting; OFDM receiver system; dual-path pipelined shared memory architecture; fast Fourier transform; memory configuration; orthogonal frequency division multiplexing; signal-to-quantization noise ratio; single-port SRAM; throughput rate; Application specific integrated circuits; Digital multimedia broadcasting; Digital video broadcasting; Energy consumption; Microelectronics; Multimedia communication; Multimedia systems; OFDM; Signal processing algorithms; Throughput; CMMB; Orthogonal frequency division multiplexing (OFDM); fast Fourier transform (FFT); low power;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351632

Filename

5351632