DocumentCode
2656009
Title
A redundant fault identification algorithm with Exclusive-OR circuit reduction
Author
Tandai, Miyako ; Shinsha, Takao
Author_Institution
Gen. Purpose Comput. Div., Hitachi Ltd., Hadano, Japan
fYear
1998
fDate
10-13 Feb 1998
Firstpage
463
Lastpage
468
Abstract
This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test pattern generation algorithm show nearly 100% fault coverage for complex arithmetic logic circuits. Moreover we achieved 99.99% fault coverage applying this algorithm with a weighted random pattern generator to the LSIs (100-450 kgates) of Hitachi MP5800 mainframe computer
Keywords
combinational circuits; fault location; logic circuits; logic testing; Exclusive-OR circuit reduction; FAN-based test pattern generation algorithm; Hitachi MP5800 mainframe computer; LSIs; complex arithmetic logic circuits; redundant fault identification algorithm; weighted random pattern generator; Arithmetic; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Fault diagnosis; Large scale integration; Logic circuits; Redundancy; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669526
Filename
669526
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