DocumentCode
2656050
Title
Fault analysis in networks with concurrent error detection properties
Author
Bolchini, C. ; Salice, F. ; Sciuto, D.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fYear
1998
fDate
23-26 Feb 1998
Firstpage
957
Lastpage
958
Abstract
The design of self-checking circuits through output encoding finds a bottleneck in the realization of the network so that each fault produces only errors detectable by the adopted code. An analysis of an expected TSC network is proposed, based on the application of the weighted observability approach. The aim is the verification of the SC property of the encoded circuit (TSC fault simulation) and identification of critical areas for a consequent manipulation to achieve a complete fault coverage
Keywords
error detection codes; fault diagnosis; logic testing; observability; redundancy; SC property; TSC network; concurrent error detection properties; fault coverage; fault simulation; output encoding; totally self-checking circuits; weighted observability approach; Boolean functions; Circuit faults; Circuit testing; Costs; Encoding; Fault detection; Intelligent networks; Network synthesis; Performance analysis; Redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655987
Filename
655987
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