Title :
Attractive line codes for high-speed LANs and MANs and their realization
Author_Institution :
IBM Zurich Res. Lab., Ruschlikon, Switzerland
Abstract :
Steadily increasing data rates in local and metropolitan area networks call for the high-speed realization of line codes. For many applications these line codes should be DC-free. The code selected for the fiber channel standard (FCS) belongs to a class of DC-free codes known as alternate codes. New DC-free line codes that improve the timing properties of the FCS code are constructed. Look-ahead precomputation and state switching are used to reduce single XOR operation. A high-speed encoder architecture for two-state alternate codes, based on state switching and parallel processing, is described, using the example of the FCS code. The architecture is well-suited to VLSI implementation. Using this architecture, the FCS code can be efficiently realized with a low-speed technology (e.g., CMOS) even at multigigabit data rates
Keywords :
VLSI; linear codes; local area networks; metropolitan area networks; parallel architectures; DC-free line codes; VLSI; fiber channel standard; high-speed LANs; high-speed MANs; high-speed encoder architecture; local area networks; metropolitan area networks; parallel processing; state switching; two-state alternate codes; ANSI standards; CMOS technology; Computer architecture; FDDI; Laboratories; Local area networks; Optical fiber devices; Standards development; State feedback; Telephony;
Conference_Titel :
Communications, 1993. ICC '93 Geneva. Technical Program, Conference Record, IEEE International Conference on
Conference_Location :
Geneva
Print_ISBN :
0-7803-0950-2
DOI :
10.1109/ICC.1993.397597