DocumentCode :
2656081
Title :
Noise characterization of the 0.35 μm CMOS analog process implemented in regular and SOI wafers
Author :
Brouk, I. ; Nemirovsky, Y.
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
fYear :
2004
fDate :
13-15 Dec. 2004
Firstpage :
171
Lastpage :
174
Abstract :
Noise measurements of the 1/f noise in p-MOS and n-MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in "regular" and SOI wafers) of the 0.35 μm CMOS process are compared and it is found that they exhibit similar 1/f noise. The results of this characterization of the 0.35 μm process are compared with the similar characterization results of the 0.5 μm CMOS process. The results of this study are useful in the design and modeling of 1/f noise of CMOS analog circuits.
Keywords :
CMOS analogue integrated circuits; MOSFET; SIMOX; flicker noise; integrated circuit noise; semiconductor device noise; 0.35 micron; 0.5 micron; CMOS analog circuits; CMOS process; MOS transistors; MOSFET; SIMOX SOI wafers; bias conditions; flicker noise; noise characterization; noise measurements; 1f noise; CMOS process; CMOS technology; Circuit noise; Frequency; Low-frequency noise; MOSFETs; Noise measurement; Semiconductor device modeling; Telegraphy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN :
0-7803-8715-5
Type :
conf
DOI :
10.1109/ICECS.2004.1399642
Filename :
1399642
Link To Document :
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