A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI

Author

Chen, H.P. ; Kuo, J.B.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

175

Lastpage

178

Abstract

The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.

Keywords

CMOS logic circuits; VLSI; bootstrap circuits; integrated circuit design; integrated logic circuits; logic design; low-power electronics; network analysis; power consumption; 0.8 V; CMOS logic circuit; adiabatic DCVS logic circuit; adiabatic differential cascode voltage switch logic circuit; bootstrap technique; capacitance coupling; clocked adiabatic latch approach; compensating transistors; energy consumption; low-power VLSI; pass transistors; true-single-phase-clocking circuit; CMOS logic circuits; Capacitance; Clocks; Coupling circuits; Latches; Logic circuits; Switches; Switching circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on

Print_ISBN

0-7803-8715-5

Type

conf

DOI

10.1109/ICECS.2004.1399643

Filename

1399643