Title :
Electrical modelling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures
Author :
Caillard, B. ; Azaïs, F. ; Nouet, P. ; Dournelle, S. ; Salomé, P.
Author_Institution :
Montpellier II Univ., France
Abstract :
This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PiN diode model for the post-triggering behaviour. As an illustration, the model has been validated against silicon in both 0.18μm and 0.13μm technologies.
Keywords :
CMOS integrated circuits; circuit simulation; electrostatic discharge; overcurrent protection; semiconductor device models; silicon; thyristors; 0.13 micron; 0.18 micron; ESD protection structure; LSCR; PiN diode model; Si; circuit-level simulation; deep submicron CMOS; electrical model; electrostatic discharge; inner currents; lateral silicon controlled rectifiers; post-triggering behaviour; CMOS integrated circuits; Electrostatic discharges; Overcurrent protection; Semiconductor device modeling; Silicon; Thyristors;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the
Print_ISBN :
0-7803-7800-8
DOI :
10.1109/BIPOL.2003.1274943
