Title :
SDNN-3: A simple processor architecture for O(1) parallel processing in combinatorial optimization with strictly digital neural networks
Author :
Nakagawa, Tohru ; Kitagawa, Hajime ; Page, Edward W. ; Tagliarini, Gene A.
Author_Institution :
Toyota Technol. Inst., Nagoya, Japan
Abstract :
An architecture for high-speed and low-cost processors based upon SDNNs, (strictly digital neural networks) to solve combinatorial optimization problems within O(1) time is presented. Combinatorial optimization problems were programmed as a set selection problem with the k-out-of-n design rule, and solved by a cluster of SDN elementary processors in a discrete operation manner of TOH (traveling on hypercube), which is a rule for synchronized parallel execution. In all simulation cases, the latest SDNN-3 hardware achieved O(1) parallel processing in solving large-scale N-queen problems of up to 1200-queens. It was confirmed that all of the solutions are optimum, and that the SDNN processor always converges to global minima without any external one
Keywords :
computational complexity; neural nets; optimisation; parallel architectures; SDNN-3; combinatorial optimization; digital neural networks; hypercube; large-scale N-queen problems; parallel processing; strictly digital neural networks; time complexity; Computational modeling; Computer networks; Hardware; Hopfield neural networks; NP-complete problem; Neural networks; Neurons; Parallel processing; Power system modeling; Stochastic processes;
Conference_Titel :
Neural Networks, 1991. 1991 IEEE International Joint Conference on
Print_ISBN :
0-7803-0227-3
DOI :
10.1109/IJCNN.1991.170755
