Architecture research and VLSI implementation for discrete wavelet packet transform

A discrete wavelet packet transform hardware design based on frame-partitioned architecture is presented in this paper. In the design of the processor, a kind of optimization technique of memory-the same address operation is proposed, which can decrease the size of the memory and raise the hardware utility efficiency. A two-buffer structure memory system is evolved to meet the real time request of the outside system, and the adoption of four-stage pipeline increases the real time data processing ability of the system. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Alter´s EP20K200E. It is demonstrated that this kind of wavelet packet transform architecture can carry out the design objectives of real time, universal, parameterized and one-chip feasible