Title :
An encoding technique for design and optimization of combinational logic circuit
Author :
Bhadra, Dipayan ; Tarique, Tanvir Ahmed ; Ahmed, Sultan Uddin ; Shahjahan, Md ; Murase, Kazuyuki
Author_Institution :
Dept. of Electr. & Electron. Eng., Khulna Univ. of Eng. & Technol. (KUET), Khulna, Bangladesh
Abstract :
A neural representation of combinational logic circuit is proposed, called `Logical Neural Network´ (LNN). LNN is a feed-forward neural network (NN) where the weights of the network indicate the connections of digital circuit. The logic operations of the circuit such as AND, OR, NOR etc are performed with the neurons of LNN. A modification of Simple Genetic Algorithm (mSGA) is applied to design and optimize the LNN for a given truth table. The proposed technique is experimentally studied on four bit parity checker, two bit multiplexer, two bit full adder, full subtractor, and two bit multiplier circuits. LNN is compared with conventional `Cell Array´ method. LNN outperforms the Cell Array method in terms of number of required gates.
Keywords :
combinational circuits; encoding; feedforward neural nets; genetic algorithms; logic design; parity check codes; bit full adder; bit multiplexer; bit multiplier circuits; bit parity checker; combinational logic circuit design; digital circuit connections; encoding technique; feed-forward neural network; genetic algorithm; logic operations; logical neural network; optimization; truth table; Arrays; Artificial neural networks; Combinational circuits; Digital circuits; Logic gates; Neurons; Optimization; Cell array; Combinational logic circuit; Design and optimization; Genetic algorithm; Logical Neural Network;
Conference_Titel :
Computer and Information Technology (ICCIT), 2010 13th International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4244-8496-6
DOI :
10.1109/ICCITECHN.2010.5723860