DocumentCode
2656618
Title
Lower the error floor of LDPC with fixed error pattern
Author
Huang, Chen ; Zhou, Liang ; Wen, Hong ; Zhao, Qian ; Xu, Fen
Author_Institution
Commun. Nation Key Lab., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Volume
3
fYear
2010
fDate
17-19 Sept. 2010
Abstract
This paper presented a FEC scheme with very high performance and high information bit rate. By analyzing the error-floor characteristics of a family of QC (Quasi-Cyclic)-LDPC codes, we design a concatenated code to eliminate this kind of trapping set which caused fixed error pattern. The simulation results have demonstrated the performance of the novel scheme is efficient. The error floor that we estimate is below 1e-15. This approach can be used on the high speed 100Gp/s communication.
Keywords
forward error correction; parity check codes; FEC; concatenated code; error floor; fixed error pattern; quasicyclic-LDPC codes; Parity check codes; EG; QC-LDPC; concatenated code; error floor; trapping set;
fLanguage
English
Publisher
ieee
Conference_Titel
Educational and Information Technology (ICEIT), 2010 International Conference on
Conference_Location
Chongqing
Print_ISBN
978-1-4244-8033-3
Electronic_ISBN
978-1-4244-8035-7
Type
conf
DOI
10.1109/ICEIT.2010.5608383
Filename
5608383
Link To Document