DocumentCode
2656694
Title
A novel capacitor-less 2-T SOI DRAM cell
Author
Zhang, Guohe ; Shao, Zhibiao ; Hu, Zhigang
Author_Institution
Xi´´an Jiaotong Univ., Xian
fYear
2007
fDate
12-14 Dec. 2007
Firstpage
1
Lastpage
2
Abstract
The capacitor in conventional 1T/1C DRAM cell accounts for large area and can hardly be realized by SOI technology. This cell can operate in low voltage, but needs super shallow junction, which is difficult to realize in process and not suitable for scaling down. In this work, a novel capacitor- less two-transistor (2-T) SOI DRAM cell is proposed for the first time.
Keywords
DRAM chips; silicon-on-insulator; capacitor-less 2-T SOI DRAM cell; dynamic random access memory; silicon on insulator; Capacitors; Educational institutions; Equivalent circuits; Impact ionization; Low voltage; MOSFET circuits; Random access memory; Threshold voltage; Tin; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium, 2007 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4244-1892-3
Electronic_ISBN
978-1-4244-1892-3
Type
conf
DOI
10.1109/ISDRS.2007.4422257
Filename
4422257
Link To Document