Design of an architecture for multiprocessor system-on-chip (MPSoC)

With the development of IC industry, system-on-chip becomes more and more complicated. Some big systems such as machine vision system require a great deal of operation, which could not be implemented well by only one processor. This paper presents an asymmetry architecture (1 master and 3 slaves) of multiprocessor SoC (MPSoC), and gives an example of its application on the machine vision system to illustrate the features, architecture and the design of this MPSoC. All the 4 processors are connected by the on-chip bus. They could be programmed and compiled separately in advance, and cooperate in the application system. The master is responsible for the control of the whole system, and it doesn´t need to know the details of the algorithms, while the slave processors only take charge of different algorithms for certain applications. When the master requires one of these algorithms, it only needs to send a simple super-instruction through the on-chip bus to the related slave. Then the slave will complete that task independently. It is a better way to implement advanced system like machine vision system with classical processors. It will improve the performance/price ratio of the system greatly and it´s very easy and convenient for application