A 150-MHz 1.25 μm CMOS/SOS DSP integrated circuit

Summary form only given. A delay and multiply chip was developed to demonstrate the performance capability of a 1.25-μm CMOS/SOS process and design methodology under stringent spacecraft environmental conditions. The chip was fabricated and exhibited correct functionality at speed on first silicon. Packaged parts were shown to operate up to a tester-limited 150 MHz at 5 V. After a total dose irradiation of 0.5 MRad, parts were found to be completely functional up to 120 MHz. The circuit exhibited a preradiation power dissipation characteristic of 0.58 μW/gate/MHz at 3.3 V, exemplifying the low power capability of this SOS technology. High-speed testing utilized a bench test set-up integrated with a built-in self-test capability which automatically generated the test vectors on-chip. The built-in test vector generation was achieved by designing the data input registers to be configurable as linear sequence generators. The timing characteristics of the circuit have been compiled and preliminary results show excellent agreement with design specifications