• DocumentCode
    2656764
  • Title

    Input-free cascode Vthn and Vthp extractor circuits

  • Author

    Wang, Yanbin ; Tarr, Garry ; Wang, Yanjie

  • Author_Institution
    Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
  • fYear
    2004
  • fDate
    13-15 Dec. 2004
  • Firstpage
    282
  • Lastpage
    285
  • Abstract
    Input-free nMOS and pMOS Vth (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted Vth for nMOS and pMOS is referenced to ground and VDD respectively. Both nMOS and pMOS Vth extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 μm CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.
  • Keywords
    MOS integrated circuits; electric potential; low-power electronics; power consumption; 0.29 mW; 0.35 micron; 0.44 mW; 2 V; 2.9 V; body effect; cascode structure; input-free threshold voltage extractor circuits; nMOS circuits; pMOS circuits; power consumption; Electric variables measurement; Equations; MOS devices; MOSFET circuits; Mirrors; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
  • Print_ISBN
    0-7803-8715-5
  • Type

    conf

  • DOI
    10.1109/ICECS.2004.1399673
  • Filename
    1399673
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2656764