A quantum mechanical model of gate leakage current for scaled NMOS transistors with ultra-thin High-K dielectrics and metal gate electrodes

This paper develops a quantum mechanical model for gate leakage current in scaled high-K metal-gate,NMOS transistors by considering both DT and TAT in low gate voltage regions,which can also be applied to other dual dielectric layer systems. The tunneling current is very sensitive to the low dielectric constant layer thickness. The proper control of the interfacial layer is important to continue CMOS device scaling.