Image correlation using a bit level systolic array

The author describes a bit-serial systolic array architecture based on simple one-bit pipelined processing cells for real-time image correlation. Due to the high sampling rates (up to 40 MHz) and the large data streams, the implementation of image processing algorithms such as two-dimensional correlation requires dedicated chips. The proposed bit-serial architecture includes an optimized scheme for inner-product computation that realizes a speed and area improvement over a previous method. A chip has been designed to compute the two-dimensional correlation function in synchronization with the scanning rate of industrial TV cameras for gray-scale TV images