A robust offset cancellation scheme for analog multipliers [utilises digital integrator]

Author

Wang, Xiaofeng ; Shi, Zhouyuan ; Sonkusale, Sameer

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

326

Lastpage

329

Abstract

A new robust offset cancellation scheme for analog multipliers is presented. The offset signal is extracted from the multiplier output using a digital integrator and is fed back to the input for cancellation. This scheme cancels the offset at both the inputs of analog multipliers. The cancellation circuitry is simple and mostly digital, so is suitable for on-chip implementation. The circuit and a Gilbert multiplier are designed in TSMC 0.18 μm CMOS technology to verify the scheme. Schematic simulation shows that the cancellation can greatly attenuate the DC offset and harmonics.

Keywords

CMOS integrated circuits; analogue multipliers; circuit feedback; comparators (circuits); error compensation; integrating circuits; mixed analogue-digital integrated circuits; 0.18 micron; CMOS; DC offset; analog multipliers; comparator; digital integrator; folded Gilbert cell multiplier; harmonics; multiplier input offset cancellation; offset cancellation scheme; output/input feedback error cancellation; Analog-digital conversion; CMOS technology; Capacitors; Circuit simulation; Computational modeling; Low pass filters; Power harmonic filters; Robustness; Sensor arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on

Print_ISBN

0-7803-8715-5

Type

conf

DOI

10.1109/ICECS.2004.1399684

Filename

1399684