• DocumentCode
    2657218
  • Title

    Comparative study of p+/n+ gate modified Saddle MOSFET and p+/n+ gate bulk FinFETs for sub-50 nm DRAM cell transistors

  • Author

    Park, Ki-Heung ; Han, K.R. ; Kim, Y.M. ; Choi, B.-K. ; Lee, Jong-Ho

  • Author_Institution
    Kyungpook Nat. Univ., Daegu
  • fYear
    2007
  • fDate
    12-14 Dec. 2007
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this work, we propose p+/n+ gate and apply it to modified saddle MOSFET and bulk FinFET to solve the problems mentioned above. We compare both devices in terms of scalability and show electric field profiles. The device characteristics are studied by using 3-D device simulator.
  • Keywords
    DRAM chips; MOSFET; nanoelectronics; p-n junctions; semiconductor device models; 3-D device simulator; DRAM cell transistors; electric field profiles; p+-n+ gate bulk FinFET; p+-n+ gate modified saddle MOSFET; scalability terms; size 50 nm; Doping profiles; Educational institutions; FinFETs; Geometry; Leakage current; MOSFET circuits; Random access memory; Scalability; Threshold voltage; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Device Research Symposium, 2007 International
  • Conference_Location
    College Park, MD
  • Print_ISBN
    978-1-4244-1892-3
  • Electronic_ISBN
    978-1-4244-1892-3
  • Type

    conf

  • DOI
    10.1109/ISDRS.2007.4422285
  • Filename
    4422285
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2657218