Modeling Verilog designs using a value-based model

Model-based diagnosis (MBD) is a well known (AI) technique for localizing faulty components in physical systems. A prerequisite for the application of model based diagnosis is the representation of the physical system as a model. Developing models for fault localization in HDL designs has been an active research area in recent years. Whereas Verilog is considered the most widely used HDL, research on fault localization has mainly focused on the VHDL domain. The research presented herein reports on a novel logical model for Verilog designs that can be automatically derived from the source program and can be directly used by a model-based diagnosis engine for computing diagnoses. We also point out some notable semantic differences between VHDL and Verilog and discuss its implications on debugging model.