• DocumentCode
    2657614
  • Title

    Lead free solder bump manufacturing with IBM´s C4NP process

  • Author

    Laine, Eric ; Ruhmer, Klaus ; Perfecto, Eric ; Longworth, Hai ; Hawken, David

  • Author_Institution
    SUSS MicroTec, Inc., Waterbury Center, VT
  • fYear
    2006
  • fDate
    27-28 June 2006
  • Firstpage
    292
  • Lastpage
    297
  • Abstract
    More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies used are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. C4NP (C4-new process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as large pitch/large ball WLCSP bumping applications
  • Keywords
    chip scale packaging; fine-pitch technology; flip-chip devices; printed circuits; solders; 300 mm; IBM C4NP process; PC board; fine pitch bumping; flip-chip in package; molten solder; solder bump manufacturing; solder paste printing; solder transfer technology; wafer level chip scale package; Chip scale packaging; Closed loop systems; Commercialization; Environmentally friendly manufacturing techniques; Glass; Lead; Manufacturing processes; Microelectronics; Printing; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06. Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    1-4244-0488-6
  • Type

    conf

  • DOI
    10.1109/HDP.2006.1707609
  • Filename
    1707609