DocumentCode
2657769
Title
Correct high-level synthesis: a formal perspective
Author
Mendías, J.M. ; Hermida, R. ; Fernández, M.
Author_Institution
Dept. de Arquitectura de Computadores y Autom., Univ. Complutense de Madrid, Spain
fYear
1998
fDate
23-26 Feb 1998
Firstpage
977
Lastpage
978
Abstract
This paper presents a formal synthesis system which delegates the design space exploration to non-formal, and potentially incorrect, high level synthesis tools. With a quadratic complexity, our system obtains either a truly correct-by-construction design, since the formal design process constitutes itself the verification process, or demonstrates that the solution found by the conventional tool was incorrect
Keywords
combinational circuits; computational complexity; formal verification; high level synthesis; design space exploration; formal synthesis system; high-level synthesis; quadratic complexity; truly correct-by-construction design; verification process; Circuit synthesis; Computer bugs; Data structures; Delay; Equations; Flow graphs; Hardware; High level synthesis; Kernel; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655997
Filename
655997
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