Title :
A bypass scheme for core-based system fault testing
Author :
Nourani, M. ; Papachristou, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a “bypass” mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem
Keywords :
application specific integrated circuits; automatic testing; directed graphs; fault diagnosis; integrated circuit testing; logic testing; ASIC cores; bypass scheme; core accessibility; core input port; core output port; core-based system fault testing; directed weighted graph; global design; patterns; shortest path problem; signatures; test data; test methodology; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Electronics industry; Integrated circuit interconnections; Semiconductor device testing; Shortest path problem; System testing; Wires;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655998
