DocumentCode
2658125
Title
A high performance data-path to accelerate DSP kernels
Author
Galanis, M.D. ; Theodoridis, G. ; Tragoudas, S. ; Soudris, D. ; Goutis, C.E.
Author_Institution
Electr. & Comput. Eng. Dept., Patras Univ., Greece
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
495
Lastpage
498
Abstract
In this paper, a high-performance data-path for accelerating DSP kernels is proposed. The data-path is based on a flexible, universal, and regular component that allows one to optimally exploiting both inter- and intra-component chaining of operations. The component is implemented as a combinational circuit and the steering logic existing inside the component allows one to easily realizing any desirable complex hardware unit - called a template - so that the data-path´s performance benefits from the chaining of operations. Due to the universal structure of the component, the synthesis of an application is accomplished by unsophisticated, yet efficient, algorithms. An average reduction of 20% in latency is achieved when a comparison with a template-based data-path is performed.
Keywords
combinational circuits; data flow graphs; digital signal processing chips; logic design; DFG; DSP kernel acceleration; combinational circuit; data flow graph; flexible computational components; high performance data-path; latency reduction; operations inter-component chaining; operations intra-component chaining; steering logic; template complex hardware unit; Acceleration; Combinational circuits; Delay; Digital signal processing; FCC; Hardware; High level synthesis; Kernel; Physics computing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN
0-7803-8715-5
Type
conf
DOI
10.1109/ICECS.2004.1399726
Filename
1399726
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