The 1:10 phased demultiplexer circuit

The behavior of the 1:10 phased demultiplexer (PDMUX10) circuit is analyzed. The circuit demultiplexes the input clock signal into ten phased output signals by streaming sets of twenty clock phases. A phase difference equal to the half period of the clock is maintained between consecutive output transitions. The VHDL description of the PDMUX10 cell is given and the simulation and synthesis results are generated. A 2-level tree-like structure is built by applying the phased outputs of the PDMUX10 cell into the corresponding clock inputs of ten cell replicas that extend the circuit behavior. An EXOR10 gate is attached to the PDMUX10 cell output ports and aggregates all the phases that the phased clock signals are carrying while preserving their phase associations.