An extra-low-frequency RS-SCALDO technique: A new approach to design voltage regulator modules

Supercapacitor-based energy recovery techniques can be coupled with low-dropout regulators to enhance the end-to-end efficiency (ETEE) of a linear regulator by multiplication factors such as 1.33, 2 or 3. For example, a 12-to-5 V supercapacitor assisted low-dropout regulator (SCALDO) theoretically achieves 84% ETEE compared to the 42% efficiency of a simple linear regulator. The experimental prototype achieved an approximate ETEE of 80%. The supercapacitor performs as a lossless voltage-dropper in this SCALDO design, cyclically absorbing energy and releasing to the low-dropout (LDO) regulator at frequencies in the order of few millihertz to a few hundreds of hertz. The reduced-switch SCALDO regulator (RS-SCALDO) is an extension of the basic SCALDO topology that improves current handling capabilities and reducing the number of power switches while combining multiple LDOs with a common output rail. VRMs can be designed with digital potentiometer-assisted voltage identification (VID) feature using the RS-SCALDO. The main focus of this paper is to provide implementation details of an RS-SCALDO circuit to design a low-noise VRM that cycles at extremely low frequencies (e.g. 1 to 500 mHz) and to present the experimental results of a 1.5 V, 5 A proof of concept prototype.