FPART: a multi-way FPGA partitioning procedure based on the improved FM algorithm

Author

Rongzheng, Zhou ; Jiarong, Tong ; Pushan, Tang

Author_Institution

Dept. of Electron. Eng., Fudan Univ., Shanghai, China

fYear

1998

fDate

10-13 Feb 1998

Firstpage

513

Lastpage

518

Abstract

In this paper, a multi-way FPGA partitioning procedure FPART is introduced. The objective function of this procedure is to reduce the number of FPGA devices and the IOB utilization. An improved min-span FM bi-partitioning algorithm on the basis of an advanced gain model is adopted as the fundamental method, and three modules: init-part, optimize, and merge are combined in FPART to approach better results. After initial partitioning, the procedure optimizes the subsets to reduce the total span of cutset and then merges some subsets by removing the cells in them. Experimental results with MCNC´93 benchmarks show that FPART is fast and efficient

Keywords

field programmable gate arrays; logic partitioning; minimisation of switching nets; FPART; FPGA; IOB utilizatiion; init-part; merge; min-span FM bi-partitioning; multi-way FPGA partitioning; optimize; Circuit testing; Costs; Delay; Field programmable gate arrays; Libraries; Partitioning algorithms; Research and development; Size control; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669539

Filename

669539