Title :
Fast high-level fault simulator
Author :
Deniziak, S. ; Sapiecha, K.
Author_Institution :
Cracow Univ. of Technol., Poland
Abstract :
A new fast fault simulation technique is presented for calculating fault propagation through high level primitives (HLPs). Reduced ordered ternary decision diagrams are used to describe HLPs. The technique is implemented in an HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators), it shows flexibility for the adoption of a wide range of fault models.
Keywords :
automatic test pattern generation; decision diagrams; fault simulation; integrated circuit testing; logic testing; system-on-chip; SOC; benchmarks; fast fault simulation technique; fault detection; fault location; fault propagation; high level primitives; high-level ATPG; high-level fault simulator; integrated circuit test methods; reduced ordered ternary decision diagrams; system-on-chip; Automatic test pattern generation; Benchmark testing; Binary decision diagrams; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Integrated circuit technology; Observability; System testing;
Conference_Titel :
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN :
0-7803-8715-5
DOI :
10.1109/ICECS.2004.1399748
