Title :
Hybrid adders for high-speed arithmetic circuits: A comparison
Author :
Aranda, Monico Linares ; Báez, Ramon ; Diaz, Oscar Gonzalez
Author_Institution :
Dept. de Electron., Inst. Nac. de Astrofis., Opt. y Electron., Puebla, Mexico
Abstract :
In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process. Performance has been also compared for different supply voltage values. The simulation results show that the Chang adder is the best in terms of PDP figure of merit; however the Aguirre adder is the best in terms of driving capability even at low power supply.
Keywords :
CMOS digital integrated circuits; adders; digital arithmetic; Aguirre adder; Chang adder; Mentor graphics environment; TSMC 180 nm CMOS process; high-speed arithmetic circuits; one-bit hybrid full adders; power consumption; Adders; CMOS integrated circuits; Conferences; Delay; Power demand; Simulation; Transistors; Adders; CMOS digital integrated circuits; VLSI; arithmetic; full adder;
Conference_Titel :
Electrical Engineering Computing Science and Automatic Control (CCE), 2010 7th International Conference on
Conference_Location :
Tuxtla Gutierrez
Print_ISBN :
978-1-4244-7312-0
DOI :
10.1109/ICEEE.2010.5608566
