Design and implementation of a 2-level sinusoidal PWM generator with modulation based harmonic elimination

In PWM, harmonie elimination has been achieved traditionally through solution of non-linear equations for switching angles and practically implemented by storing offline calculated solutions in ROM and then reading them in real time. This imposes large memory problems for systems like ac. machines requiring flexibility both in amplitude and frequency. A modified carrier based naturally sampled PWM approach that closely approximates the performance of harmonic elimination solved this problem in [1]. The modified approach can produce even lower weighted total harmonic distortion than conventional harmonic elimination, and supports dynamic PWM with low harmonics This paper presents flexible design and efficient implementation of such a scheme with minimum hardware resources. The system was prototyped using SystemC, implemented using VHDL and verified on Xilinx Spartan 3E FPGA.