DocumentCode :
2659264
Title :
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
Author :
Hirata, Hiroaki ; Kimura, Kozo ; Nagamine, Satoshi ; Mochizuki, Yoshiyuki ; Nishimura, Akio ; Nakase, Yoshimori ; Nishizawa, Teiji
Author_Institution :
Matsushita Electric Industrial Co., Ltd., Japan
fYear :
1992
fDate :
1992
Firstpage :
136
Lastpage :
145
Keywords :
Computer graphics; Delay; Job shop scheduling; Laboratories; Multiprocessing systems; Multithreading; Permission; Reduced instruction set computing; Throughput; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on
Print_ISBN :
0-89791-509-7
Type :
conf
DOI :
10.1109/ISCA.1992.753311
Filename :
753311
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2659264
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