Sub-nanosecond digital phase shifter for clock synchronization applications

This paper describes a digital circuit capable of performing sub-nanosecond phase shifting over a wide range of clock frequencies. In this circuit metastability phenomena and clock jitter generate glitches during the down-converted digital clock state transitions. In the work reported here, such glitches are removed using three deglitching techniques described in the paper. The phase shifter is implemented and tested in an FPGA custom made board designed for a timing network application and its performance is assessed experimentally.