DocumentCode
2659876
Title
Seamless - A Latency-Tolerant RISC-Based Multiprocessor Architecture
Author
Fineberg, S.A. ; Casavant, T.L. ; Pease, B.H.
Author_Institution
University of Iowa
fYear
1992
fDate
1992
Firstpage
432
Lastpage
432
Keywords
Cities and towns; Computer architecture; Delay; Genetic programming; Hardware; Laboratories; Message passing; Multithreading; Parallel processing; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on
Print_ISBN
0-89791-509-7
Type
conf
DOI
10.1109/ISCA.1992.753349
Filename
753349
Link To Document