Power reduction in pipelines

Author

Parameswaran, Sri ; Guo, Hui

Author_Institution

Dept. of Comput. Sci. & Electr. Eng., Queensland Univ., Brisbane, Qld., Australia

fYear

1998

fDate

10-13 Feb 1998

Firstpage

545

Lastpage

550

Abstract

The reduction of power consumption for a system level pipeline is addressed in this paper. The pipeline is composed of several stages. Each stage has several behaviours. Different behaviours have differing execution times. The speed of the pipeline is only affected by the behaviours on the critical path of the slowest stages. Other behaviours can be slowed down to decrease the power consumed in the system. We propose a multi-voltage supply scheme, in which differing behaviours are supplied with differing voltages. The formulas for computing the supply voltage of each behaviour and minimal power consumption are derived in this paper. The results of computer experiment show that up to 80% hardware power can be saved with this scheme

Keywords

computer power supplies; parallel architectures; pipeline processing; power consumption; hardware power; minimal power consumption; multi-voltage supply scheme; power consumption; system level pipeline; Computer science; Energy consumption; Frequency; Hardware; Histograms; Pipelines; Power dissipation; Power engineering computing; Resource management; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669548

Filename

669548