Material choice for optimum stress memorization in SOI CMOS processes

Author

Gehring, A. ; Mowry, A. ; Wei, A. ; Wiatr, M. ; Boschke, R. ; Javorka, P. ; Mulfinger, B. ; Scott, C. ; Lenski, M. ; Koerner, G. ; Huy, K. ; Otterbach, R. ; Klais, J. ; Geisler, H. ; Mantei, T. ; Greenlaw, D. ; Horstmann, M.

Author_Institution

AMD Saxony LLC & Co., Dresden

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

1

Lastpage

2

Abstract

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals are found to play an important and partially very different role for these two improvement mechanisms.

Keywords

MOSFET; annealing; hardness; silicon-on-insulator; stress effects; CMOS technology; SOI CMOS processes; SOI CMOS transistors; Si-SiO₂; anneal sequences; film hardness; material properties; optimum stress memorization; stress engineering; Annealing; CMOS process; CMOS technology; Capacitance; Degradation; Educational institutions; Optical materials; Silicon on insulator technology; Surface-mount technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2007 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-1891-6

Electronic_ISBN

978-1-4244-1892-3

Type

conf

DOI

10.1109/ISDRS.2007.4422444

Filename

4422444