Floating-Gate MOSFET parallel analog network for assignment problems

Floating-Gate-MOS Transistor (FGMOSFET) has several applications on analog circuit design; in some cases FGMOSFET simplifies high-complexity circuits because of its inherent properties. On the other side, working with FGMOSFET on subthreshold regime has allowed non-linear function implementation such as exponential and natural logarithm functions. Moreover, working on subthreshold regime is one of the most useful techniques for low-power designs. Taking advantage of FGMOSFET´s properties, this work shows an analog CMOS circuit that finds the best solution of the combinatorial task of assignments in terms of Lagrange multipliers. This is in contrast to the Hopfield paradigm, which is often VLSI-costly. The building block in this circuit uses FGMOSFET transistors, has low silicon complexity and exhibits good electrical performance according to PSpice simulations. Final simulations were developed for a 0.5μm CMOS technology and the output currents reach an optimal solution in all cases. It might include threshold voltage programming circuits for reducing mismatch effects.