Title :
VLSI system compiler for digital signal processing: modularization and synchronization
Author :
Itoh, Kazuhito ; Kunieda, Hiroaki
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
An overview is presented of a VLSI system compiler which generates highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms. In line with this overview, a description is given of a modularization and a synchronization of general digital signal processing algorithms which convert them into suitable forms for implementation by a processor array on a VLSI chip
Keywords :
VLSI; circuit layout CAD; computerised signal processing; digital signal processing chips; parallel algorithms; parallel architectures; synchronisation; CAD; VLSI chip; VLSI system compiler; digital signal processing; fast processor array; general DSP algorithms; highly parallel array; layout design; modularization; synchronization; Digital signal processing; Digital signal processing chips; Frequency; Parallel processing; Routing; Signal generators; Signal processing algorithms; Systolic arrays; Transfer functions; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112448
