Title :
A 10-bit 1-GHz 33-mW CMOS ADC
Author :
Sahoo, Bibhu Datta ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles, CA, USA
Abstract :
A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; analogue-digital conversion; capacitors; operational amplifiers; 4-bit first stage; CMOS ADC; CMOS technology; capacitor mismatch; frequency 490 MHz; noise figure 52.4 dB; one-stage op amp; pipelined ADC; size 65 nm; CMOS integrated circuits; Calibration; Capacitors; Frequency measurement; Gain; Gain measurement; Operational amplifiers;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243774
