An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements

Author

Majidzadeh, Vahid ; Schmid, Alexandre ; Leblebici, Yusuf ; Rabaey, Jan

fYear

2012

fDate

13-15 June 2012

Firstpage

36

Lastpage

37

Abstract

A pulsed UWB transmitter (Tx) using finite impulse response synthesis of the raised-cosine pulse is presented. Symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) for aggressive duty-cycling of the Tx. The chip is fabricated with 90nm CMOS technology and consumes 540 μW from 1 V power supply resulting in 45 pJ/bit energy efficiency with -26 dBm of output power.

Keywords

CMOS analogue integrated circuits; delay lock loops; power amplifiers; pulse position modulation; radio transmitters; radiofrequency amplifiers; transient response; ultra wideband technology; AD-DLL; CMOS technology; PA elements; aggressive duty-cycling; all-digital delay locked loop; energy efficiency; finite impulse response synthesis; power 540 muW; power amplifier elements; pulse position modulator; pulsed UWB transmitter; raised-cosine pulse synthesis; size 90 nm; symmetric pulse combining technique; voltage 1 V; Calibration; Computer architecture; Delay; Delay lines; Image edge detection; Modulation; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243777

Filename

6243777