Title :
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture
Author :
Matsunaga, Shoun ; Miura, Sadahiko ; Honjou, Hiroaki ; Kinoshita, Keizo ; Ikeda, Shoji ; Endoh, Tetsuo ; Ohno, Hideo ; Hanyu, Takahiro
Author_Institution :
Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan
Abstract :
A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.
Keywords :
CMOS memory circuits; MOSFET; MRAM devices; content-addressable storage; integrated logic circuits; magnetic tunnelling; memory architecture; 12T-SRAM TCAM cell circuit; 16T-SRAM-based TCAM cell circuit; 4T-2MTJ-cell fully parallel TCAM cell circuit; CMOS technology; four-MOS-transistor; high-density fully parallel nonvolatile TCAM; logic function; nonvolatile logic-in-memory architecture; nonvolatile logic-in-memory structure; nonvolatile storage function; size 100 nm; size 90 nm; standby-power-free nonvolatile TCAM; ternary content-addressable memories; transistor counts; two-MTJ-device cell circuit; CMOS integrated circuits; Computer architecture; Magnetic tunneling; Microprocessors; Nonvolatile memory; Transistors; Wires;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243781
