A multiprocessor architecture for circuit simulation

Circuit simulation uses a substantial amount of computation time to simulate a large circuit. A multiprocessor architecture can provide a cost effective way of speeding up the inner loop of the algorithm. A parallel processing architecture for circuit simulation algorithms that is designed as an accelerator system for workstations is presented. The architecture allows the inner loop of the circuit simulation algorithm, assembling the equations that describe the circuit and solving them, to be executed at high speed. It solves the large sets of equations using LU decomposition, which is both accurate and robust. The way in which the algorithms are supported by the distributed memory architecture and how this is reflected in the architecture´s implementation are discussed