Hardware realization of discrete convolution using CORDIC and Vedic multiplier

In Digital Image Processing, the discrete linear convolution is used as a basis for linear filtering. In this paper, the multiplier operation involved in discrete linear convolution operation using CORDIC and Vedic algorithm is implemented on FPGA Spartan XC3S1000 device. Performance evaluation of these two approaches is done and the trade off in terms of Area, Power and Speed is tabulated. It is seen that the CORDIC Algorithm has almost 80% advantage in Area and 95 % advantage in Speed over the Vedic algorithm. Depending on the performance metrics to be optimized, algorithm can be chosen.