Title :
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
Author :
Chan, Chi-Hang ; Zhu, Yan ; Sin, Sai-Weng ; U, Seng-Pan ; Martins, R.P.
Author_Institution :
State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China
Abstract :
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration.
Keywords :
analogue-digital conversion; digital-analogue conversion; CMOS technology; bit rate 1 Gbit/s; compact DAC structure; custom-designed DAC array; interleaving SAR ADC; low parasitic layout structure; on-chip offset calibration; power 3.8 mW; segmentation switching; size 65 nm; successive-approximation-register analog-digital converters; voltage 1 V; Arrays; Calibration; Capacitors; Layout; Metals; Switches; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243802
